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IC(Integarated Circuit)
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IC(Integarated Circuit)
MACOH-E/V
(Enhanced version of MAC Over HDLC Packet Forwarding Engine)
Recently there have been increasing needs for high performance and cost-effective remote access solutions. The xDSL system is one of the most popular solutions for the internet access application. Most modems and WAN transceivers have synchronous serial interface for the customer lines. On the other hand, IEEE 802.3 Ethernet with CSMA/CD is the most common in LAN applications. Hence, the gateway between Ethernet LAN and synchronous serial WAN is mandatory for the remote access applications.
The MAC over HDLC packet forwarding engine (MACOH) is designed so that the solution may be achieved simply and cost-effectively. MACOH is a one-chip solution for LAN(Ethernet) to WAN(HDLC) packet forwarding engine which supports wire speed operation. It supports 10/100 Mbps Ethernet and up to 50Mbps synchronous HDLC interface. The master and slave modes of the reduced media independent interface (RMII) are provided for the interface with Ethernet PHY and switch device.
¡ß¡ß Features ¡ß¡ß
¢ºCompliant IEEE 802.3 MAC with RMII
(Reduced Media Independent Interface)
- 10/100 Mbps Full and Half-duplex CSMA/CD MAC
- Supports both master and slave RMII (to a PHY or switch port)
- Preamble, SFD detection and generation
- Autopadding undersize packets to meet the minimum packet size requirements
- CRC32 generation and detection
- Oversize, undersize, allignment, and CRC error detection/discarding
- Maintains a minimum interframe gap
- MII Management (MDC, MDIO)
- IEEE 802.3x flow control
¢ºIEEE 802.1d MAC filtering
- Real-time filtering with 256 address table
- Automatic address learning and aging
¢ºHDLC serial WAN interface
- Full-duplex serial transmit and receive up to 50Mbps link
- Synchronous HDLC packet format
- CRC16 generating and checking
- Bit stuffing and destuffing
- Flag, Idle, and Abort sequence handling
- Oversize, allignment, and CRC error detection/discarding
- Ethernet loopback for testing
- Configurable rising / falling clock edge operation
- Error-reporting to an external processor
¢ºSubscribers control functions
- Automatic source MAC address limitation in the HDLC link
- Configurable HDLC Tx traffic rate control
- CPU custom message communication through HDLC link
¢ºDRAM controller
- Configurable packet-buffering in EDO DRAM
- Up to 340 packet-buffering capacity
¢ºSPI (CPU interface)
- Slave SPI with fixed 8-bit data transfer mode
- Supports burst read and write modes
- Access to the performance monitoring registers (packet counters)
- Interrupt request
¢º9 LED displays
¢ºLow power, 3.3 Volt supply
¢º100 pin QFP package
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[Contact Information] |
| Posted by |
Mihee Lee
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| e-Mail | This information shows after Login. |
Firm
| Intigate Inc.
| | Address | #1304,SeoulVentureTown,679-5 Yeoksam-Dong,Gangnam | City & ZIP
| Seoul, Korea
| Land
| NULL
| Telephone
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| | Interest | exporting |
| | Product Specifications | |
| | Industry Category | Electrical Components |
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| | My Offers | |
| | Other Products | |
| | Customers | Worldwide |
| | Company History | we are manufacturer and exporter of non-memory semicondutor with high technology in Korea.
we are intrested in export our products to your country through your company.
your favorable reply would be appreciated. |
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| Product Details |
| Product id |
112 |
| views |
1006 |
| Added |
2003.09.17 |
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